1. Field of the Invention
The invention relates in general to systems for verifying integrated circuit (IC) designs, and in particular to a system for debugging power-aware IC designs.
2. Description of Related Art
An IC that is not designed to conserve power can use up to ten times more power than an IC of similar capability that is designed to conserve power. Low-power design not only increases the battery usage for mobile devices but also improves system reliability and lowers the cost of packaging. Low-power techniques such as clock-gating, gate-optimization, multi-VDD, and multi-threshold have been studied for decades and been proved to be effective at reducing dynamic power consumption. However, as manufacturing processes continue to advance, leakage power consumption has begun to play a more critical role in power consumption. Power management (PM) techniques such as power-shutoff (PSO), and dynamic voltage frequency scaling (DVFS), multi-voltage design, and power aware memories can be more effective to reduce both dynamic and leakage power consumption.
Power Shutoff (PSO), also called “power gating”, involves temporarily shutting down a section of an IC not currently in use to halt power dissipation in that section. An IC designer partitions an IC into several “power domains” (or “power islands”), each power domain having a separate primary power supply. The power supply to a “gated” power domain can be turned off so that the devices in that power domain do not consume power when they are not needed. Before switching off the supply to a gated power domain, it may be necessary to store data indicating states of various signals within that domain so the stored data can be used for resetting devices within that domain to their last states when the domain's power is restored. An IC may therefore include memory devices (“retention cells”) to store such data while a gated power domain's supply is off. A gated power domain may also require “isolation cells” to isolate one or more of the domain's output ports from the external environment when the domain's power is off to prevent those output ports from supplying floating inputs to devices in active power domains that can drive those devices to unexpected states. An IC having gated power domains will include a special controller for turning on and off gated power domains under appropriate conditions and for controlling each domain's retention and isolation cells.
A multi-voltage IC is organized into various “voltage domains” that receive differing supply voltages. Since both the speed and power dissipation of a circuit device increase with its supply voltage, devices that must work at high speed receive the full supply voltage while devices that can operate more slowly can operate at reduced voltages. Supplying each device with only the voltage it needs reduces overall power consumption. A multi-voltage design employs special buffers (“level-shifters”) to shift logic levels of signals crossing voltage domain boundaries. A multi-voltage IC may employ dynamic Voltage and Frequency Scaling (DVFS), also known simply as Dynamic Voltage Scaling (DVS), a technique for temporarily reducing both the voltage and clock frequency of devices within a voltage domain in order to reduce energy consumption when high-speed operation is not needed. In such cases, the IC's power controller must be able to signal the domains level-shifters to accommodate the changes in supply voltage.
Power Definition Markup Language
Since adding power gating, multi-voltage domains or dynamic voltage and frequency scaling late in the design process, at a low gate level of abstraction, can introduce unanticipated bugs in the design, an IC designer should try to plan power management at the register-transfer-level (RTL) or earlier architecture stage of the IC design process.
Although designers typically employ a hardware description language (HDL) to describe an IC design, HDL lacks the capability to model power management. Designers now use Power Definition Markup Languages (PDML) to compensate the lack of power modeling capability in HDL. PDML enables a designer to incorporate a design's “power-intent” into each level of design abstraction by specifying power and DVFS domains, by indicating signals requiring state retention, isolation and level shifting, and by specifying the manner in which such power management devices are to be controlled.
PDML focuses only on the power related aspects of a design by inferring a virtual power network that is parallel to the HDL design and working in tandem with it, but which is not a part of the HDL design itself. Hence it is not necessary to modify an HDL language description of an IC to provide power-aware capability to a circuit design. PDML models can overlay power-aware behaviors onto an HDL design and allow verification systems to verify those behaviors. Thus PDML provides a high-level abstract model of the intended power management behavior for use when the IC design is at a high level of abstraction, and it also allows a designer to subsequently match the specified behavior to devices implementing that power behavior[k1]
Verification
An IC designer can compile an HDL/PDML design and various instructions into a testbench program for a logic simulator that simulates the response of the IC to a specified input signal pattern. The simulator generates and stores value change data representing the behavior of selected circuit signals so that the designer, employing a debugging tool processing the value change data, can determine whether an IC constructed in accordance with the HDL design will behave as expected. A debugging tool can display waveforms representing signal behavior, HDL code, and schematic diagrams representing the HDL design and can annotate the waveform, code and schematic diagram displays to relate signal behavior to portions of the HDL design that are responsible for that signal behavior.
A conventional logic simulator can take into account a PDML model of the IC when it simulates and HDL design by connecting the PDML model to clock, reset, power on/off and other power control signals of the HDL design. Those signals tell the PDML model when to trigger power-aware behavior by telling the simulator when to change normal RTL behavior to reflect results of power control network activity. For example, if a power domain is shutoff at a particular time during a logic simulation, the PDML model will tell the HDL simulator to cancel all events within that power domain and force values of signals within that domain as “unknown”. Thus an HDL simulator can impose the power intent specified by the PDML description on the circuit behavior of the HDL design during a logic simulation run thereby allowing a designer to verify whether the simulated IC behavior satisfies the specified power intent.
Even though a simulator can take into account the power intent of a PDML when simulating IC behavior, it can be difficult and time-consuming for a designer to debug an HDL design having associated PDML power-intent. When employing a conventional debugging tool to debug an HDL design, the designer loads the HDL design and the logic simulation output data into the debugging tool and then uses the debugging tool to trace through the design to determine why various signals may take on unexpected values at various times during the logic simulation. Since traditional debugging tools don't take the PDML aspects of a design into consideration, designers must manually cross reference the HDL and PDML designs to determine whether an unexpected signal value is caused by a defect in the HDL design or by PDML introduced effects. Debugging an HDL/PDML design can therefore be tedious and error-prone, particularly when the HDL and PDML aspects of a design are developed by different design teams at different stages of the design process.
What is needed is a debugging tool that takes the PDML portion of an HDL/PDML design into account to make it easier for a designer to determine the causes of unexpected circuit behavior.
The present invention relates to an automated power-aware debugging system for a hardware description language (HDL) integrated circuit design having a corresponding power-intent described in a Power Definition Markup Language (PDML).